Regviz

RISC-V /Machine Cause (64-bit mcause)

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as Machine Cause (64-bit mcause)

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/RISC-V/Machine Cause (64-bit mcause)#0x0

63 6059 5655 5251 4847 4443 4039 3635 3231 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Instruction address misaligned / Reserved)Exception Code0 (Interrupt)Interrupt

Exception Code=Instruction address misaligned / Reserved

Fields

Exception Code

0 (Instruction address misaligned / Reserved): undefined

1 (Instruction access fault / Supervisor software interrupt): undefined

2 (Illegal instruction / Reserved): undefined

3 (Breakpoint / Machine software interrupt): undefined

4 (Load address misaligned / Reserved): undefined

5 (Load access fault / Supervisor timer interrupt): undefined

6 (Store/AMO address misaligned / Reserved): undefined

7 (Store/AMO access fault / Machine timer interrupt): undefined

8 (Environment call from U-mode / Reserved): undefined

9 (Environment call from S-mode / Supervisor external interrupt): undefined

11 (Environment call from M-mode / Machine external interrupt): undefined

12 (Instruction page fault / Reserved): undefined

13 (Load page fault / Counter-overflow interrupt): undefined

15 (Store/AMO page fault / Reserved): undefined

16 (Double trap / Reserved): undefined

17 (Reserved / Reserved): undefined

18 (Software check / Reserved): undefined

19 (Hardware error / Reserved): undefined
Interrupt